Semiconductor processing has resulted in increasingly complex and powerful integrated circuits. By scaling down device size and employing improved materials, circuit power consumption continues to be reduced and operating speeds increased.
Large scale integrated circuits are now commonly utilizing multilevel metallization schemes involving two or more patterned conductive layers, each conductive layer being separated by insulation layers. The conductive layers are connected by vertically extending via structures. The combination of conductive layers and via structures creates the "wiring pattern" for the integrated circuit.
Prior art methods accomplish vertical, conductive interconnects between metallization layers using by depositing metal into an etched hole. These methods typically begin with the deposition of the first metallization layer. The first metallization layer is patterned, typically by creating an etch mask using photolithographic techniques, and subsequently etching the first metallization layer. The etch mask is stripped and the patterned layer is covered with a deposited dielectric. Via holes are then etched through the dielectric layer to the first metallization layer and filled with a conductive material. Prior art methods accomplish this step by a number of different methods. One prior art method involves depositing a first conductive layer over the dielectric layer and into the hole. The resulting structure includes a first metal line, a via hole and a second metal line that extends into the via hole. Unfortunately, the depth of via holes can result in poor step coverage, particularly at the bottom of the via hole. The lack of adequate step coverage leads to high resistance or "opens" between the metal layers, which can degrade circuit performance.
When manufacturing metallization patterns of very small geometries, structures using via holes to electrically connect a top and bottom conductive pattern also have the drawback of requiring an overlay. An overlay is a widening of the lower conductive pattern where a via hole is anticipated, to ensure the via hole will be properly aligned with the lower conductive layer. Overlays reduce the minimum packing density of patterns by forcing greater spaces between adjacent lines in a conductive pattern.
Another method of providing a conductive via structure between metallization layers is discussed in U.S. Pat. No. 5,202,579 issued to Fuji et al. Similar to the first prior art method described above, the '579 patent describes a process of depositing a tungsten film and subsequently etching back that film to produce a buried tungsten plug. The '579 patent, due to the reactivity between aluminum and tungsten, requires a complex sandwich layer structure of titanium and titanium nitride, tungsten, and then a second titanium and titanium nitride layer. Such complex metallization schemes can increases process complexity and processing time.
A third prior art method is taught in U.S. Pat. No. 5,192,713 issued to Yusuke Harada. The '713 patent utilizes a selective chemical vapor deposition (CVD) process to deposit tungsten in a via hole while doping another via hole with arsenic to retard the formation of a tungsten plug. The selective tungsten CVD process requires a particular types of substrate, typically polysilicon, and often requires an entire deposition system dedicated solely to depositing tungsten. This can increase processing time and be a costly method of creating viable via structures between metallization layers.
None of the prior an addresses the need for a simple via structure and contact manufacturing process that produces repeatable via structures having low resistance and that accomplishes these ends without excessive equipment costs.